Conroe

I guess the fall IDF was when I first dug up some details on Intel's new Core architecture. Once I heard one specific detail, I knew that Intel was going to take the performance crown back with that processor, and that AMD's glory days were soon to be over. Yet for some reason most people just won't accept it. Why is it so hard to accept the fact that Intel has learned from their mistakes in the past?

Since I haven't really done a piece on Conroe, I guess I should talk abit about what it is before diving into why this processor will be the greatest thing we've seen since the Opteron was launched. The basic underpinnings of a processor are designed to last several years, with minor updates fueling sales. Usually these updates include atleast one or two die shrinks, addition of new instruction sets, and cache increases. With the Pentium 4, Intel did more than it's share of updates to try and get Netburst to perform as expected. First we had front side bus updates, which are more of a platform update than anything. Bus speeds went from 400mhz effective all the way to 1066mhz with the Extreme Editions. Memory went from the failed Rambus to DDR, then to DDR2. Caches went from 512kb to 2mb. SSE2 and SSE3 were added. Hyperthreading was brought to the table, and lastly the pipeline was stretched out a bit more to attempt to hit the holy grail of 4.0ghz. Intel honestly could have easily released >4.0ghz products, however the move away from clock speed killed that initiative. It is all about marketing in the end, and releasing a 4ghz product when the megahertz race was called off would've hurt their ability to sell Pentium-M's and Core processors.

So that brings us up to the newest technology from Intel, commonly known as the Core architecture. Intel has realized that clock speed will not be enough to compete with AMD's processors, and they have gone back to the last product they launched that was actually well received by the media, the Penitum M. Basically an updated Pentium III, the Pentium M brought a low-wattage, short pipelined processor that performed well compared to AMD's offering on the laptop side. Ever since then, AMD has struggled to keep up with Intel in mobile applications, and I believe that Centrino is the way to go with any mobile device. With the launch of Yonah, aka Core Solo and Core Duo, Intel raised the bar just a little higher, and the now dated Turion cannot deliever anywhere near the performance that you can get with a Core Duo system.

 With Conroe, Intel has seriously raised the bar. The framework for this Core processor was laid down back in the early 90's with the Pentium Pro. That architecture survived through the Pentium II, and Pentium III processors, and was truly wonderful IMO. The key to the performance was an advanced Out-Of-Order instruction pipeline, good branch prediction, and quality cache setups. The new Core architecture takes these things one step further, and while I could just start rambling about macro and micro instructions and things of that nature, I'll try to keep everything nice and simple.

The basic workings inside a processor involve the cache and an instruction pipeline. Instructions, or functions for lack of a better description, are created by the operating system and sent to the BIOS to be handed off to the processor. These are usually stored in RAM and grabbed by the processor when there is available space in the outter-most cache of the processor, in most cases the L2 cache. The instructions and their corresponding data are kept there until the processor can squeeze them into the instruction pipeline. So if you ask a processor to add 1 + 1, that is translated by the OS, handed to the BIOS, and then sent along it's merry way until a cycle opens up for it to be completed. The result, 2, is sent back to the cache where the BIOS hands it back to the OS which draws it on your screen. Pretty intense, but try to hold on here.

Back to the point, at IDF last fall, Intel told us one specific thing that would change the way I looked at AMD for a long time. See, the internals of the instruction pipeline are what makes a processor really tick. The Netburst architecture in it's final iteration had a massively long pipeline, 31 stages, which meant that less work was being done per clock. Each stage takes one cycle to complete, or one hert, so by making the processor do less work per cycle, Intel figured clock speeds could go through the roof. At the launch of Netburst, 10ghz was in the not too far away future. AMD kept away from the fight, and kept their pipelines in the mid teens, where I believe it should belong. Intel has now come back, and Conroe will feature a 14 stage pipeline. This will take away those long pauses that occur with the current Pentium 4.

What's really interesting is in the actual math units on the core. Kind of like pixel pipelines on a GPU, processors have math units that do the dirty work. There is usually one capable of handling floating point operations, and 2 that can handle standard additions and subtractions. Intel has raised the bar, and now 4 operations can be done per clock. That should give an immediate 33% boost in performance, just like adding a pixel shader would make a GPU faster. To add to this boost, Intel has made some major jumps in instruction bundling. Processors bundle instructions that are easy to do together in what is refered to as Micro-Ops fusion. Basically, once an instruction has been decoded, they can be bundled and shipped through together. Intel has added Macro-ops fusion to the core, allowing non-decoded instructions to be bundled together as well. Add to this the fact that all SSE instructions can now be performed in one cycle, and we've got a winner.

So if you didn't catch all of that, I apologize. I also apologize for any inaccuracies in the above description. Trying to take out some of the details to get to the point can do that sometimes.  What you should take away is that the upcoming Conroe, Woodcrest, and Merom will be able to not only run pretty fast, but they will be able to do more work per megahertz. This can be a staggering increase in the case of SSE instructions and simple arithmetic instructions. The testing that was done at this most recent IDF proves out what has been said all along. A 4-issue core will beat out a 3-issue core all day, and I've been saying it for a while now.

Now, how can AMD shape up? It should actually be pretty easy, but then again I don't design processors. Buy adding another issue to the pipeline, and maybe stretching it out a bit to get more megahertz, AMD could pretty easily come back. Just toss in another ALU, advance the cache-sharing, and enable support for the macro-ops fusion, and you're there. Intel still does not have an integrated memory controller, so until they pull that off, AMD has a chance. The recently discussed K8L may just do that for AMD. Then there's the coprocessor idea that I spoke about earlier. It appears that AMD may just go ahead and stick a floating-point specific processor in as one of the cores of their quad-core processors coming up. Things are good, and getting better every day.